Memory manufacturing process with bitline isolation
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United States of America Patent
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Mar 18, 2014
Grant Date -
Oct 9, 2003
app pub date -
Apr 8, 2002
filing date -
Apr 8, 2002
priority date (Note) -
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Abstract
A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.
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