Router and methods using in-band link between managing processor and routing processor

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United States of America Patent

SERIAL NO

10284655

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Abstract

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A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction. The nonvirtual transaction accomplishes the intent of the virtual transaction but operates on an actual network port, for example, a storage device.

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Patent Owner(s)

Patent OwnerAddress
QLOGIC CORPORATION3545 HARBOR BOULEVARD COSTA MESA CA 92628 COSTA MESA CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Norman Diamond Bar, CA 10 1184
Edmonds, Tracy Morgan Hills, CA 12 1166
Hill, Rexford San Diego, CA 9 1207
How, Stephen San Diego, CA 7 1362
Jeong, Wayland Agoura Hills, CA 13 947
Kodama, Jean Cerritos, CA 12 1571
Muliadi, Harun Thousand Oaks, CA 9 1092
Nishimura, Michael San Diego, CA 8 1211
Peterson, Eric Russell Camarillo, CA 6 1078
Terrell, William C Thousand Oaks, CA 14 1249

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