CMOS transistor on thin silicon-on-insulator using accumulation as conduction mechanism
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United States of America Patent
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Issued Date -
Oct 30, 2003
app pub date -
Apr 15, 2003
filing date -
Apr 18, 2000
priority date (Note) -
Abandoned
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Abstract
A transistor structure fabricated on a thin silicon-on-insulator layer. The transistor comprises: a body formed in a silicon layer of a first dopant type; a gate structure formed atop the body; a source adjacent a first edge of the gate structure formed of the first dopant type; and a drain adjacent a second edge of the gate structure formed of the first dopant type.
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