Circuit and method for accelerating the test time of a serial access memory device
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United States of America Patent
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Issued Date -
Nov 13, 2003
app pub date -
May 9, 2002
filing date -
May 9, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A serial memory device includes a test mode for accelerating the writing of externally-supplied data into the memory array by ganging column address so that a single clock writes a single row. Data is retrieved from the memory either by singularly addressed locations or by mirrored address locations across a memory boundary with retrieved data being individually compared via logic asserted during testing operations. Depending on the requested test mode, the compare results can return an order for continuance of array testing or insertion of complemented data into the currently-compared memory location and continuance of array testing. A GO/No Go indication is provided via output circuitry controlled by the test mode.
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