Arbitration logic for assigning input packet to available thread of a multi-threaded multi-engine network processor
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United States of America Patent
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Issued Date -
Dec 18, 2003
app pub date -
Apr 28, 2003
filing date -
Jun 4, 2002
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A network processor having a plurality of processing engines and packet assignment logic operable to selectively assign the received packets to the processing engines is disclosed. The packet assignment logic of the network processor distributes the received packets according to at least in part the packet size of previously distributed packets. In one embodiment, the packet assignment logic does not assign any packets to a processing engine that is already assigned a 'large' packet. In this way, load balancing among the processing engines is improved, resulting in a higher performance network processor.
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