High-speed chip-to-chip communication interface
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United States of America Patent
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Feb 20, 2007
Grant Date -
Dec 25, 2003
app pub date -
May 16, 2003
filing date -
Jun 4, 2002
priority date (Note) -
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Abstract
A high-speed parallel interface for communicating data between integrated circuits is disclosed. The interface is implemented by a transmitter and receiver pair and a single-ended parallel interconnect bus coupling to the transmitter and receiver pair. As opposed to transmitting small swing signals over differential signal lines, the transmitter transmits data to the receiver at full swing over the single-ended parallel interconnect bus. The invention can be implemented with simple CMOS circuitry that does not consume large die area. Accordingly, many link interfaces can be implemented on a single chip to provide a large data bandwidth.
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