Method and apparatus for adjusting DRAM signal timings

United States of America Patent

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Issued Date
Jan 1, 2004
app pub date
Jun 26, 2002
filing date
Jun 26, 2002

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Abandoned

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Abstract

A method and apparatus for adjusting memory signal timings by shifting the timing of a clock signal generated by a memory controller relative to the time at which other signals begin to be transmitted by the memory controller.

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Patent Owner(s)

Patent Owner	Address
INTEL CORPORATION A DELAWARE CORPORATION	2200 MISSION COLLEGE BLVD SANTA CLARA CA 95052

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G06F:ELECTRIC DIGITAL DATA PROCESSING

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Inventor Name	Address	# of filed Patents	Total Citations
Bodas, Amit	Folsom, CA	3	117
Bogin, Zohar B	Folsom, CA	7	175
Freker, David E	Sacramento, CA	14	466
Ramanathan, Girish P	Rancho Cordova, CA	2	48
Ramaswamy, Sridhar	Folsom, CA	77	2152

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Method and apparatus for adjusting DRAM signal timings

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United States of America Patent

10185886

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APP PUB NO	20040003194A1
SERIAL NO	10185886
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10185886

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