Integrated circuit package for semiconductor devices with improved electric resistance and inductance
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United States of America Patent
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Jan 11, 2005
Grant Date -
Jan 8, 2004
app pub date -
Jul 2, 2002
filing date -
Jul 2, 2002
priority date (Note) -
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Abstract
A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a 'L' shape, a 'C' shape, a 'J' shape, an 'I' shape or any combination thereof.
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