Importance

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Abstract

A chip select circuit is based on a multiplexed bus having a chip select phase, an address phase, and a data phase. During the chip select phase, a chip select latch receives chip select signals from the multiplexed bus at one input and a chip select enable signal at a second input. The chip select latch has a plurality of outputs to the chip select inputs of a plurality of connected devices. Based on the chip select signals from the multiplexed bus, one of the plurality of outputs enables a selected connected device. During the address phase, an address latch receives address signals from the multiplexed bus at a first input and an address enable signal at a second inputs. The output of the address latch passes the address signals to the address inputs of the plurality of connected devices. The chip select circuit is operative to used the multiplexed bus to select one of the connected devices using the single chip select enable signal without requiring further enabling/control signals.

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