Duty cycle corrector
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United States of America Patent
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Apr 19, 2005
Grant Date -
Jan 22, 2004
app pub date -
Jul 18, 2002
filing date -
Jul 18, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.
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