Heterogeneous interconnection architecture for programmable logic devices
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United States of America Patent
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Dec 7, 2004
Issued Date -
N/A
app pub date -
May 30, 2003
filing date -
Oct 12, 1999
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Expired
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Abstract
An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.
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