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Abstract

A multiple CAM chip architecture for a CAM memory system is disclosed. The CAM chips are arranged in a diamond cascade configuration such that the base unit includes an input CAM chip, two parallel CAM chip networks, and an output CAM chip. The input CAM chip receives a CAM search instruction and provides the search instruction and any match address simultaneously to both CAM chip networks for parallel processing of the search instruction. Each CAM chip network provides the highest priority match address between the match address of the input CAM chip and its own match address. The output CAM chip then determines and provides the highest priority match address between the match addresses of both CAM chip networks and its own match address. Each CAM chip network can include one CAM chip, or a plurality of CAM chips arranged in the base unit diamond cascade configuration. Because the clock cycle latency of the diamond cascade configured CAM memory system is determined by sum of the inherent CAM chip search latency and the number of parallel levels of CAM chips, many additional CAM chips can be added to the system with a sub-linear increase in the system latency.

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First Claim