Uniform testing of tristate nets in logic BIST
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United States of America Patent
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Jul 19, 2005
Grant Date -
Feb 5, 2004
app pub date -
Jul 31, 2002
filing date -
Jul 31, 2002
priority date (Note) -
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Abstract
A built-in-self-test (BIST) circuit is discussed for selecting tristate nets with substantially uniform distribution using a tristate testing control device (TTCD). The circuit allows the deterministic testing of tristate nets in the context of pseudo-random BIST. A feedback shift register is described that activates a single tristate or set of tristate at a time in order to avoid bus contention. Another TTCD embodiment uses a counter and decoder. A test mode switching unit (TMSU) coupled between the TTCD and the tristate net selects test or functional mode for tristate enables. Parallel multiplexers are discussed as one embodiment of a TMSU. Another TMSU embodiment describes even better test coverage. A method, which may be performed on a distributed computer system, is discussed for identifying tristate nets within a net-list and adding a TTCD and a TMSU to the net-list.
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