Method for forming a metal interconnection layer of a semiconductor device using a modified dual damascene process
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 9, 2006
Grant Date -
Feb 26, 2004
app pub date -
May 30, 2003
filing date -
Aug 1, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an interconnection pattern having a dual damascene structure. A dielectric material such as copper is deposited on the interconnection pattern, which is planarized through CMP, thereby forming a via contact having a single damascene structure without a recess therein.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully