System and method for deterministic communication across clock domains
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United States of America Patent
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Sep 19, 2006
Grant Date -
Mar 11, 2004
app pub date -
Sep 6, 2002
filing date -
Sep 6, 2002
priority date (Note) -
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Abstract
A clock distribution and control system (10) includes one counter (30) in a clock generation domain and another counter (40) in a phase-delayed clock domain. The phase-delayed domain counter (40) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.
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