Failure analysis system, failure analysis method, a computer program product and a manufacturing method for a semiconductor device
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United States of America Patent
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N/A
Issued Date -
Mar 11, 2004
app pub date -
Jun 30, 2003
filing date -
Sep 9, 2002
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A failure analysis system, includes a chip position calculation module configured to calculate fault chip positions of a plurality of circuit blocks in a chip region based on layout information on the circuit blocks positioned in the chip region and fault information on the circuit blocks; a wafer position calculation module configured to calculate fault wafer positions in a wafer based on the fault chip positions and position information showing a chip region layout in a wafer plane; and a mapping module configured to perform a mapping display of the fault wafer positions in accordance with physical coordinates on the wafer plane.
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