Circuit for protection against electrostatic discharge
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United States of America Patent
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N/A
Issued Date -
Mar 25, 2004
app pub date -
Sep 25, 2002
filing date -
Sep 25, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method and system for protecting RF circuits from ESD events are disclosed that unlike traditional diode-train-based ESD protection circuit's high turn-ON voltage, provide various voltage levels for triggering one or more ESD shunt path. The disclosed ESD protection circuit employs one or more small diodes arranged in a series to trigger ON one or more current carrying transistors that once switched ON, conduct high current. The ESD protection circuit rapidly shunts the ESC current thereby reducing the impact of the ESD event upon the protected RF circuit. Furthermore, the disclosed system and method exhibit a reduced parasitic loading effect with the use of small triggering diodes and large current carrying transistors in a diode configuration. The disclosed method and system provide a simple and compact ESD protection circuit capable of providing customized protection against reverse ESD events as well.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| ANADIGICS INC | 141 MT BETHEL RD WARREN NJ 07059 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Sun, Maoyou | Piscataway, NJ | 2 | 24 |
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| Fee | Large entity fee | small entity fee | micro entity fee | due date |
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| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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