High -frequency scan testability with low-speed testers
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United States of America Patent
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Issued Date -
May 6, 2004
app pub date -
Oct 30, 2002
filing date -
Oct 30, 2002
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A clock generation circuit for providing high-frequency scan testability with a low-speed tester includes a clock selector and control logic. The clock selector receives a reference clock signal and a high-frequency clock signal and produces an output signal selected from the reference clock signal and the high-frequency clock signal based on a clock selector control signal. The control logic that receives a capture signal and produces the clock selector control signal to modify the clock selector output signal in response to the capture signal. The clock selector output signal may be used to provide high-frequency scan testability with a low-speed tester.
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