Via programmable gate array interconnect architecture
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United States of America Patent
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Issued Date -
Jun 3, 2004
app pub date -
Aug 8, 2003
filing date -
Aug 9, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A segmentation architecture for wiring segments which provides interconnections for a gate array integrated circuit is described. Programming is provided by selectable vias between wiring segments and to the semiconductor substrate surface. The wiring segments of two interconnection layers are arranged in two directions and a programmable buffer can drive signals in a selectable direction depending upon how the via contacts are made to the buffer by the wiring segments carrying the buffer signals.
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