Apparatus for memory communication during runahead execution
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United States of America Patent
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Issued Date -
Jul 1, 2004
app pub date -
Dec 31, 2002
filing date -
Dec 31, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Processor architectures, and in particular, processor architectures with a cache-like structure to enable memory communication during runahead execution. In accordance with an embodiment of the present invention, a system including a memory; and an out-of-order processor coupled to the memory. The out-of-order processor including at least one execution unit, at least one cache coupled to the at least one execution unit; at least one address source coupled to the at least one cache; and a runahead cache coupled to the at least one address source.
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