Multi-stack chip size packaging method
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United States of America Patent
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May 20, 2008
Grant Date -
Aug 5, 2004
app pub date -
Dec 30, 2003
filing date -
Dec 30, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding. A potting solution is coated on the substrate and the second chip and installed thereon a heat spreader and then cured. An encapsulation resin is coated on a bottom surface of the substrate and electrically interconnected a third chip to the bottom surface of the substrate through a bump and an inner lead bump.
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