Priority queue architecture for supporting per flow queuing and multiple ports
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United States of America Patent
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Issued Date -
Aug 5, 2004
app pub date -
Oct 20, 2003
filing date -
Oct 21, 2002
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A shared memory switch architecture provides per-flow queuing that achieves high memory bandwidth and makes efficient use of memory. The memory of the memory switch is dynamically allocated to each port based on real-time traffic conditions. The priority of the packets is represented by queuing elements having a priority level determined by a weighted fair queue algorithm and its variants. The priority arbitration of queuing elements is made according to a two level hierarchy to increase the speed of priority queue management and therefore the switching throughput.
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