Importance

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Abstract

An invention for a memory core cell is provided. The memory core cell includes a storage cell, which is connected to differential writing circuitry. In addition, the storage cell is connected to single ended reading circuitry. In one aspect, the differential writing circuitry can include a pair of write bitlines coupled to the storage cell by a pair of write access transistors, with each write access transistor having a gate coupled to a write wordline. Also, the signal ended read circuitry can include a read transistor having a gate coupled to the storage element, a first terminal coupled to a read access transistor, and a second terminal coupled to ground. Further, the read access transistor can include a first terminal coupled to a read bitline, a second terminal coupled to the first terminal of the read access transistor, and a gate coupled to a read wordline.

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First Claim