DDR clocking
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United States of America Patent
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Jan 30, 2007
Grant Date -
Aug 19, 2004
app pub date -
Aug 15, 2003
filing date -
Feb 18, 2003
priority date (Note) -
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Abstract
A sampling device includes a first delay circuit and a second delay circuit in a parallel configuration, where the first delay circuit and the second delay circuit are responsive to a clock signal. A data sampling circuit may use an output of the first delay circuit and an output of the second delay circuit to sample a data signal synchronized with the clock signal. The data signal and the clock signal may be synchronized according to a double data rate (DDR) protocol.
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