Importance

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Abstract

A control interface scheme provides for communicating control information between integrated circuits (ICs) in a wireless communication chipset. A serial 3-wire bus is configured to communicate a series of control words assembled on a digital IC to an analog IC prior to a data portion of a frame used by the wireless communication chipset in communicating data. The control words include control settings for use by the analog IC during the data portion of the frame. The control settings, which are stored in registers on the analog IC, include gain settings for two receivers and a transmitter, as well as phase lock loop (PLL) control information and power management information. Several timing signals generated on the digital IC are used by the analog IC during the data portion of the frame to select among the registers to obtain the appropriate control settings at the appropriate times. By sending all such control settings to the analog IC prior to the data portion of the frame, the PLLs on the analog IC are not disturbed.

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First Claim