Dual time sliced circular bus
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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N/A
Issued Date -
Sep 9, 2004
app pub date -
Jan 27, 2003
filing date -
Jan 27, 2003
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A dual time sliced circular bus extending in opposite directions, and optionally interspersed so as to reduce noise. The width of the buses can either be dynamic or static depending upon the particular implementation. Circulating on each of the buses is a predetermined number of data structures for either transmitting an address operation or data. Each of the cores can use the data structures for transmitting and receiving data between themselves according to a transmitting and receiving scheme.
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