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Abstract

A delay locked loop (DLL) circuit in a synchronous dynamic random access memory includes a phase comparison signal generating circuit for generating a phase comparison reference signal by receiving a clock signal, wherein the phase comparison reference signal maintaining a first logic level longer than one period of a clock signal through a clock dividing operation, a delay chain for delaying an inverted phase comparison reference signal in response to a delay chain adjusting signal, a delay model for compensating a delay of a internal circuit by receiving an output signal of the delay chain and a phase comparator for comparing phase of the phase comparison reference signal and an output signal of the delay model.

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