Minimization of clock skew and clock phase delay in integrated circuits
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United States of America Patent
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Issued Date -
Oct 7, 2004
app pub date -
Apr 1, 2003
filing date -
Apr 1, 2003
priority date (Note) -
Abandoned
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Abstract
A hierarchal block for an integrated circuit includes a plurality of sequential registers, a plurality of clock cluster buffers, and a plurality of clock pins. The sequential registers are grouped into a plurality of clusters. Each of the clock cluster buffers is associated with a respective one of the clusters such that a clock net connection can be made to a clock gate input of each of the registers in the respective one of the clusters. Each of the clock pins is associated with a respective one of said clock cluster buffers such that a clock net connection can be made between each clock pin and the respective one of the clock cluster buffers.
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