Low-power cache and method for operating same
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United States of America Patent
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Issued Date -
Oct 7, 2004
app pub date -
Apr 3, 2003
filing date -
Apr 3, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A cache is provided that comprises a plurality of cache blocks that are independently selected using a direct-mapped cache access, with each block capable of storing a plurality of cache lines and having a plurality of outputs. The cache further includes comparison logic associated with each of the plurality of cache blocks, each comparison logic having a plurality of inputs for receiving the plurality of outputs of the associated cache block and configured to compare the plurality of outputs of the associated cache block with a value on a portion of an address bus that is input to the cache. Finally, the cache includes output logic for outputting from the cache an output from the comparison logic that is associated with a selected cache block. A related method for caching data is also provided.
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