Low-power decode circuitry for a processor
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United States of America Patent
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Issued Date -
Oct 14, 2004
app pub date -
Apr 10, 2003
filing date -
Apr 10, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A processor having improved decode logic is provided. In accordance with one embodiment, the processor includes a first decoder capable of decoding a first plurality of instructions, a second decoder capable of decoding a second plurality of instructions, and special instruction logic for implementing at least one special instruction, the at least one special instruction being an instruction that the first decoder or second decoder is not designed to directly decode for execution by an execution unit in the processor. In another embodiment, a related method is provided for decoding a processor instruction.
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