Timing ring mechanism

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20040205753A1
SERIAL NO

10642336

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Abstract

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A method and system for scheduling threads and timer mechanisms of events in a computer system that includes a central processing unit (CPU), a plurality of input/output (I/O) devices, such devices as storage devices, network interface devices (NIDs) and a memory which is typically used to store various applications or other instructions which, when invoked enable the CPU to perform various tasks the timer structure provides a ring structure and an associated control block is provided. The timer mechanism of the present invention comprises a ring structure that includes an array of ring slots, with the slots relating to pointers for implementing a circular array of LIFO (Last In, First Out) queues generally where each LIFO queue maintains a listing of EventDescriptors that relate to functions which must be performed during the time slot associated with the particular pointer position.

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Patent Owner(s)

Patent OwnerAddress
GLOBESPAN VIRATA INC100 SCHULZ DRIVE RED BANK NJ 07701

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Moore, Mark Justin Cambridge, GB 16 987

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