Chip package structure
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United States of America Patent
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-
Jun 6, 2006
Grant Date -
Oct 28, 2004
app pub date -
Jan 5, 2004
filing date -
Apr 22, 2003
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.
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