Application-specific testing methods for programmable logic devices
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United States of America Patent
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May 10, 2005
Issued Date -
N/A
app pub date -
May 25, 2004
filing date -
Aug 7, 2001
priority date (Note) -
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Abstract
Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.
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