Propagation delay adjustment circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20040217794A1
SERIAL NO

10427557

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Disclosed is a method and apparatus for variably and independently delaying the rising and falling edges of a digital waveform including a dual polarity output buffer, a first delay circuit, a second delay circuit and a recombination circuit. The dual polarity output buffer outputs a first signal that is a substantial replica of the input signal and a second signal that is an inversion of the input signal. The first delay circuit is connected to the dual polarity output buffer and generates a first time delay in the rising edges of the first, non-inverted signal. The second delay circuit is also connected to the dual polarity output buffer and generates a second time delay in the rising edges of the second, inverted signal. The recombination circuit is connected to both the first delay circuit and the second delay circuit and combines the outputs thereof to generate a composite output signal representing the input signal with both the rising edges thereof and the falling edges thereof delayed independently.

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Patent Owner(s)

Patent OwnerAddress
EDC BIOSYSTEMS INC871 FOX LANE SAN JOSE CA 95131

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Strysko, Mark Mooresville, NC 1 36

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