Self-aligned trench MOS junction field-effect transistor for high-frequency applications
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United States of America Patent
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Apr 12, 2005
Grant Date -
Nov 25, 2004
app pub date -
Dec 20, 2002
filing date -
Dec 20, 2002
priority date (Note) -
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Abstract
A trench JFET includes sidewall oxide spacers at the top of the gate trench and oxide spacers at the bottom of the trench. The source terminal is located at the top surface of the chip and the drain is located at the bottom surface of the chip. The gate may include doped polysilicon, a Schottky metal, or a combination thereof. The sidewall spacers and the top of the trench increase the packing density of the device, and the spacers at the bottom of the trench reduce the gate-to-drain capacitance and prevent dopant from the gate from spreading downward towards the drain. This allows the epitaxial layer to be very thin. The JFET can be operated at high frequency and requires a very low gate drive. It is well suited, therefore, for use in a switch-mode DC--DC converter.
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