Digital clock recovery circuit employing fixed clock oscillator driving fractional delay line
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United States of America Patent
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Issued Date -
Jan 20, 2005
app pub date -
Jul 15, 2003
filing date -
Jul 15, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A clock recovery scheme for a digital communication receiver has a fixed fractional delay line that is driven by a fixed frequency reference clock source, to provide a plurality of respectively offset phase delayed versions of the reference clock. A phase lock loop, to which the received signal is coupled, controllably steps through the phase delayed versions of the reference clock, so as to controllably increase or decrease the effective frequency of the reference clock and thereby produce a recovered clock signal.
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