Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells
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United States of America Patent
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Mar 22, 2005
Grant Date -
Jan 27, 2005
app pub date -
Aug 20, 2004
filing date -
Sep 6, 2002
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Abstract
Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.
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