Synchronous stack bus for fast Ethernet repeater
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United States of America Patent
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Jun 13, 2006
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app pub date -
Aug 25, 2004
filing date -
Sep 10, 1997
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Abstract
Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.
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