SDRAM memory device with an embedded NAND flash controller
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United States of America Patent
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Jul 6, 2010
Grant Date -
Feb 3, 2005
app pub date -
Nov 12, 2003
filing date -
Jul 31, 2003
priority date (Note) -
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Abstract
A memory device includes two dies. A first memory is fabricated on one die. A controller of the first memory is fabricated on the other die. Also fabricated on the other die is another component, such as a second memory, that communicates with a host system using a plurality of signals different from the signals used by the first memory. The device includes a single interface for communicating with the host system using only the respective signals of the second component. In a most preferred embodiment, the first memory is a NAND flash memory and the second memory is a SDRAM.
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