NRAM bit selectable two-device nanotube array
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United States of America Patent
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Sep 13, 2005
Grant Date -
Feb 24, 2005
app pub date -
Mar 26, 2004
filing date -
Mar 28, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A non-volatile memory array includes a plurality of memory cells, each cell receiving a bit line, word line, and release line. Each memory cell includes a cell selection transistor and a restore transistor with first, second and third nodes. Each cell further includes an electromechanically deflectable switch, the position of which manifests the logical state of the cell. Each cell is bit selectable for read and write operations.
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