Digital delay elements constructed in a programmable logic device
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United States of America Patent
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Issued Date -
Mar 3, 2005
app pub date -
Aug 28, 2003
filing date -
Aug 28, 2003
priority date (Note) -
Abandoned
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Abstract
A delay circuit. In one embodiment, a programmable logic device (PLD) is used to implement one or more delay circuits having a plurality of delay elements. Included in the plurality of elements are a balanced number of logic elements such that rising and falling edges of a signal passing through the delay circuit propagate with substantially the same amount of delay. The delay circuit may also include a selector circuit coupled to select an output from one of the plurality of delay elements. The delay circuit may be implemented such that it preserves the duty cycle and/or pulse width of signals to which the delay is applied.
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