Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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N/A
Issued Date -
Mar 3, 2005
app pub date -
Oct 10, 2003
filing date -
Aug 28, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A mechanism for processing in a processor enabled to support and execute multiple program threads includes a parameter for scheduling a program thread and an instruction disposed within the program thread and enabled to access the parameter. When the parameter equals a first value the instruction, when issued by a program thread, reschedules the program thread in accordance with one or more conditions encoded within the parameter.
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