Clock distribution networks and conductive lines in semiconductor integrated circuits
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United States of America Patent
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app pub date -
Oct 1, 2004
filing date -
Apr 18, 2002
priority date (Note) -
Abandoned
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Abstract
A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.
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