Dual mask capacitor for integrated circuits
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United States of America Patent
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May 24, 2005
Grant Date -
Mar 24, 2005
app pub date -
Sep 24, 2003
filing date -
Sep 24, 2003
priority date (Note) -
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Abstract
An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrodes 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.
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