Method and system for controlling memory accesses to memory modules having a memory hub architecture
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United States of America Patent
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Jul 24, 2007
Grant Date -
Mar 24, 2005
app pub date -
Oct 12, 2004
filing date -
Aug 29, 2002
priority date (Note) -
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Abstract
A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.
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