Prefetch mechanism for use in a system including a host connected to a plurality of memory modules via a serial memory interconnect
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United States of America Patent
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Issued Date -
Mar 31, 2005
app pub date -
May 10, 2004
filing date -
May 13, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A system includes a host coupled to a serially connected chain of memory modules. In one embodiment, the host includes a memory controller that may be configured to issue a memory read request for data stored within the memory modules. The memory controller may further request that data be prefetched from the memory modules by encoding prefetch information within the memory read request. The memory controller may also be configured to issue a memory write request to write data to the memory modules and to selectively request that one or more pages of memory within a given one of the memory modules remain open by encoding the prefetch information within the memory write request.
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