Method and apparatus for debug support for individual instructions and memory locations
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United States of America Patent
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N/A
Issued Date -
Mar 31, 2005
app pub date -
Sep 30, 2003
filing date -
Sep 30, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method, apparatus, and computer instructions in a data processing system for monitoring processing of instructions and memory locations. An instruction is received in the data processing system for execution. If an enabled state is present, a determination is made whether the instruction is associated with an indicator in a shadow memory. A selected action is performed in response to the indicator being associated with the instruction. Responsive to being in an enabled state when a data access to a memory location occurs, a determination is made as to whether the memory location is associated with an indicator in a shadow memory. A selected action is performed in response to the indicator being associated with the memory location.
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