Continuous self-verify of configuration memory in programmable logic devices
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United States of America Patent
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Issued Date -
Mar 31, 2005
app pub date -
Sep 30, 2003
filing date -
Sep 30, 2003
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A programmable logic device (PLD) such as an FPGA or CPLD is supplementally configured to verify the integrity of its configuration data during operation of the device. The programmable logic device includes a checksum calculation engine to calculate a checksum based upon the configuration data. A checksum comparator compares the calculated checksum to a previously-calculated checksum to verify the integrity of the configuration data.
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