Method for discrete gate sizing in a netlist

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United States of America Patent

APP PUB NO 20050081175A1
SERIAL NO

10683628

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Abstract

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A set of gate sizes for a netlist having a plurality of gates wherein for each of the gates a number of discrete gate sizes is available is selected such that the selection minimizes worst slack in the netlist. A current gate size for each gate is selected and an a current weight assigned to each one of the timing edges in the netlist. A new gate size is selected for each one of the gates from one of the current gate size and second one of the available gates sizes wherein such selection of each new gate size minimizes a sum of weighted delays obtained over all timing edges. The minimum sum of weighted delays is obtained from a min-cut in a timing flow graph. The results of the min-cut are used in the next iteration and re-iterating occurs until an exit criteria is determined.

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Patent Owner(s)

Patent OwnerAddress
AMMOCORE TECHNOLOGY INCSUITE 180 1190 SARATOGA AVENUE SAN JOSE CA 95129

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lapinskii, Viktor San Jose, CA 2 18
Scott, William Franson Sunnyvale, CA 2 17

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