Error-detecting encoding and decoding apparatus and dividing apparatus

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United States of America Patent

PATENT NO 7428693
APP PUB NO 20050097432A1
SERIAL NO

10970859

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Abstract

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Disclosed are an error-detecting encoding apparatus for creating parity bits by error-detecting encoding processing, appending the parity bits to an input data string and encoding the data string, and an error-detecting decoding apparatus for detecting error using these parity bits. Data segmenting means segments an input data string, which is to undergo error-detecting encoding, into a plurality of sub-data strings, dividing means divides the segmented sub-data strings by a polynomial, which is for generating an error-detecting code, and calculates remainders, converting means applies conversion processing, which conforms to a segmentation position of the sub-data strings, to the remainders on a per-remainder basis, and combining means combines converted values, which have been obtained by the conversion processing, and outputs parity bits. An encoder appends this parity to a data string, and a decoder detects error using this parity.

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Patent Owner(s)

  • FUJITSU LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nakamura, Takaharu Kawasaki, JP 60 743
Obuchi, Kazuhisa Kawasaki, JP 185 1899
Yano, Tetsuya Kawasaki, JP 271 2943

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